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FY95 Progress Statement

Fiscal 1995 Project Portfolio Report

Charles Molnar and Ivan Sutherland (s)
charles.molnar@eng, ivan.sutherland@Eng.Sun.COM(s)

Overall Objective

To explore the potential of asynchronous concepts and technology in microprocessor and computing system design, and to provide Sun Microsystems with knowledge and expertise in this area. Such knowledge would permit Sun to take initiatives in asynchronous product design earlier with greater confidence, and with proprietary advantage over competitors who might undertake similar initiatives.

Subgoals:

To explore the Sproull Pipeline Processor architecture to a depth and detail that can establish the feasibility of an asynchronous implementation, and permit an accurate estimate of its potential performance and design difficulty.
To refine methodologies for specification, circuit synthesis, and simulation suitable for asynchronous design.
To seek broad patent protection for methods and designs.
To explore the practical issues of implementation by designing and building prototype subsystems that will test and demonstrate the approach.
To evaluate the results of the design effort so as to identify areas where asynchronous techniques have potential major advantage.
To present and explain our methods and results within the Sun community, and to cooperate with others at Sun in building value from our knowledge.
To identify relevant and promising academic work and individuals, and facilitate their interaction with Sun.

Objective for FY95

To make a detailed design for an asynchronous SPARC processor, and to explore applications of asynchronous techniques to microprocessor systems more broadly.

Description

We started the year with a proposed design for an asynchronous implementation of the Sproull Pipeline Processor. We reported last year that we thought it to be about as fast as possible. Nevertheless, during this year we made major revisions to the design as we learned how better to use fine grain concurrency to improve performance. While it is easy to design an asynchronous system that does several tasks sequentially, it has proven to be much harder to tease out concurrency to obtain high speed performance. Understanding concurrency turns out to be much harder than understanding asynchrony. People who work on operating system software and real time system design face similar difficulties.

Accomplishments

During the year, we have come to appreciate several exciting new opportunities for concurrency. The result of our work is a design in which some parts, operating in advance, establish data pathways that are later used to do computation.

We have learned much about the behavior and properties of arbiters. Different forms of arbiters start and report the results of their arbitration process in different ways. The appropriate choice of arbiter forms can have a major impact on the delays imposed on the system for arbitration. The main refinements to our system this year have come from our improved understanding of how to make arbitration concurrent with other operations.

Another step forward involves a fresh look at the control of latches in FIFOs and pipeline processors. We have further refined the stage control circuit mentioned in last year's report.

We completed an experiment contrasting "four phase" signaling with the "two phase" signaling we favor. Although the four phase technique provided a small speed advantage, the difficulty it presented in design has discouraged us from using it, except in situations where the overall architecture is very clear and stable.

We have experimented with simulations of several designs, observing their performance on specific benchmark programs represented as trace files. These simulations have been key to focusing our attention on those parts of the design most in need of improvement.

In order to understand the operation of our simulators, we have built two tools that display the behavior of simulated systems. One of them, Data-View, plots the activity of a pipeline as a static picture. The plot is a series of horizontal bars, each of which records the period during which a particular datum occupied a particular stage. The pattern of bars in adjacent stages reveals the flow of information through the pipeline. The other, VIZ, displays a motion picture of the pipeline in action. The input for both Data-View and VIZ is a journal file produced by any of our simulators. Data-View is written in C, and VIZ is written in Tcl/Tk. Tcl/Tk made it relatively easy to obtain the dynamic view presented by VIZ.

References

Presentations

International Symposium on Advanced Research in Asynchronous Circuits and Systems. Utah Conference. A special session devoted to our activity. Ivan Sutherland-Keynote; other presentations by Bob Sproull, Charles Molnar, Bill Coates, Jon Lexau, and Ian Jones.

"The Sproull Pipeline Processor." At Imperial College, University of Manchester, Cambridge University, Stanford University, Sun Microsystems, Inc., UCLA, Santa Clara University, University of Washington, Carnegie Mellon University, MIT, Yale University, and Copenhagen University.

Publications

Molnar, Charles E. and Huub Schols. "The Design Problem SCPP-A." SML-95-0138.

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