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| United States Worldwide |
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Processor ResearchFiscal 1995 Project Portfolio Report
Robert Yung
robert.yung@eng.sun.com
Overall ObjectiveTo investigate means to optimize register file accesses in a high-scalar, highly-pipelined general purpose processor architecture. This resulted in a technique called "Register Scoreboard and Caching," and a number of related patent applications. We have given several talks at SunLabs, SPARC Technology Business (STB), and worked with the processor development team in incorporating some of these ideas in the design. A paper was accepted and will be published in the International Conference of Computer Design (ICCD-95).
ReferencesPublicationsYung, R. "A 200 Mhz 4-Scalar Single-Chip Microsprocessor." Proceedings of ISSCC'95 (March 1995). Yung, R. "UltraSPARC: The Next Generation Superscalar 64-bit SPARC." Proceedings of COMPCON'95 (April 1995). Yung, R. "The Visual Instruction Set (VIS) in UltraSPARC." Proceedings of COMPCON'95 (April 1995). Yung, R. and N. Wilhelm. "Caching Processor General Registers." International Conference of Computer Design (ICCD'95) (1995). Patents Issued
Title: Rapid Data Retrieval from Data Storage Sructures using Prior
Access Predictive Annotations
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